A.5 GIC signals
The processor uses a range of signals for global disable, base address definition, interrupt types, and
Distributor messaging.
This interface exists only if the processor is configured to use the GIC CPU interface. However, the first
seven signals in the following table are present even when the processor is configured without a GIC
CPU interface.
Table A-4 GIC signals
Signal Direction Description
nFIQ[CN:0] Input
FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:
0
Activate FIQ interrupt.
1
Do not activate FIQ interrupt.
The processor treats the nFIQ input as level-sensitive. The nFIQ input must be asserted until
the processor acknowledges the interrupt.
nIRQ[CN:0] Input
IRQ request input lines. Active-LOW, level sensitive, asynchronous interrupt request:
0
Activate interrupt.
1
Do not activate interrupt.
The processor treats the nIRQ input as level-sensitive. The nIRQ input must be asserted until
the processor acknowledges the interrupt.
nSEI[CN:0] Input
System Error Interrupt request. Active-LOW, edge sensitive:
0
Activate SEI request.
1
Do not activate SEI request.
The processor treats nSEI as edge-sensitive. The nSEI signal must be sent as a pulse to the
processor.
Asserting the nSEI input causes one of the following to occur:
• Asynchronous Data Abort, if taken to AArch32. The DFSR.FS field is set to indicate an
Asynchronous External Abort.
• SError interrupt, if taken to AArch64. The ESR_ELx.ISS field is set.
nVFIQ[CN:0] Input
Virtual FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:
0
Activate FIQ interrupt.
1
Do not activate FIQ interrupt.
The processor treats the nVFIQ input as level-sensitive. The nVFIQ input must be asserted
until the processor acknowledges the interrupt. If the GIC is enabled by tying
GICCDISABLE LOW, nVFIQ must be tied off to HIGH. If the GIC is disabled by tying
GICCDISABLE HIGH, nVFIQ can be driven by an external GIC in the SoC.
A Signal Descriptions
A.5 GIC signals
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
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