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0b11 Full access.

If Advanced SIMD and floating-point are not implemented, this field is RES0.

The Advanced SIMD and floating-point features controlled by these fields are:

• Floating-point instructions.

• Advanced SIMD instructions, both integer and floating-point.

• Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-

Q15.

• FPSCR, FPSID, MVFR0, MVFR1, MVFR2, FPEXC system registers.

If the cp11 and cp10 fields are set to different values, the behavior is the same as if both fields

were set to the value of cp10, in all respects other than the value read back by explicitly reading

cp11.

cp10, [21:20]

Defines the access rights for CP10, that control the Advanced SIMD and floating-point features.

Possible values of the fields are:

0b00 Access denied. Any attempt to access Advanced SIMD and floating-point registers or

instructions generates an Undefined Instruction exception. This is the reset value.

0b01 Access at EL1 only. Any attempt to access Advanced SIMD and floating-point registers

or instructions from software executing at EL0 generates an Undefined Instruction

exception.

0b10 Reserved.

0b11 Full access.

If Advanced SIMD and floating-point are not implemented, this bit is RES0.

The Advanced SIMD and floating-point features controlled by these fields are:

• Floating-point instructions.

• Advanced SIMD instructions, both integer and floating-point.

• Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-

Q15.

• FPSCR, FPSID, MVFR0, MVFR1, MVFR2, FPEXC system registers.

[19:0]

Reserved, RES0.

To access the CPACR:

MRC p15,0,<Rt>,c1,c0,2 ; Read CPACR into Rt

MCR p15,0,<Rt>,c1,c0,2 ; Write Rt to CPACR

Table B1-35 CPACR access encoding

coproc opc1 CRn CRm opc2

1111 000 0001 0000 010

B1 AArch32 system registers

B1.41 Architectural Feature Access Control Register

reserved.

B1-207

Non-Confidential

ARM Cortex-A35 User Manual

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