ARM Cortex-A35 User Manual

EL3 exception handling:
0x2 Instructions can be executed at EL3 in AArch64 or AArch32 state.
EL2 handling, [11:8]
EL2 exception handling:
0x2 Instructions can be executed at EL2 in AArch64 or AArch32 state.
EL1 handling, [7:4]
EL1 exception handling. The possible values are:
0x2 Instructions can be executed at EL1 in AArch64 or AArch32 state.
EL0 handling, [3:0]
EL0 exception handling. The possible values are:
0x2 Instructions can be executed at EL0 in AArch64 or AArch32 state.
To access the ID_AA64PFR0_EL1:
MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt
Register access is encoded as follows:
Table B2-47 ID_AA64PFR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0100 000
The EDPFR can be accessed through the external debug interface, offset 0xD20.
B2 AArch64 system registers
B2.54 AArch64 Processor Feature Register 0, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-451
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English