ARM Cortex-A35 User Manual

0x1 Two levels of shareability implemented.
OuterShr, [11:8]
Indicates the outermost shareability domain implemented:
0x1 Implemented with hardware coherency support.
PMSA, [7:4]
Indicates support for a Protected Memory System Architecture (PMSA):
0x0 Not supported.
VMSA, [3:0]
Indicates support for a Virtual Memory System Architecture (VMSA).
0x5 Support for:
• VMSAv7, with support for remapping and the Access flag.
• The PXN bit in the Short-descriptor translation table format descriptors.
• The Long-descriptor translation table format.
To access the ID_MMFR0:
MRC p15,0,<Rt>,c0,c1,4 ; Read ID_MMFR0 into Rt
Register access is encoded as follows:
Table B1-63 ID_MMFR0 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 100
B1 AArch32 system registers
B1.80 Memory Model Feature Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-282
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English