ARM Cortex-A35 User Manual

EL3 exception handling:
0x2 Instructions can be executed at EL3 in AArch64 or AArch32 state.
EL2 handling, [11:8]
EL2 exception handling:
0x2 Instructions can be executed at EL2 in AArch64 or AArch32 state.
EL1 handling, [7:4]
EL1 exception handling. The possible values are:
0x2 Instructions can be executed at EL1 in AArch64 or AArch32 state.
EL0 handling, [3:0]
EL0 exception handling. The possible values are:
0x2 Instructions can be executed at EL0 in AArch64 or AArch32 state.
The EDPFR[31:0] can be accessed through the external debug interface, offset 0xD20.
The EDPFR[63:32] can be accessed through the external debug interface, offset 0xD24.
C8 Memory-mapped debug registers
C8.6 External Debug Processor Feature Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English