0b010 L2 cache.
L2 cache is the last level of cache that must be cleaned or invalidated when cleaning or
invalidating to the point of unification for the Inner Shareable shareability domain.
If the processor is implemented without an L2 cache, or if BROADCASTINNER is
set to 0, then LoUIS is 0b001, indicating the L1 cache.
[20:9]
Reserved, RES0.
Ctype3, [8:6]
Indicates the type of cache if the processor implements L3 cache:
0b000 L3 cache not implemented.
If software reads the Cache Type fields from Ctype1 upwards, after it has seen a value of 0b000,
no caches exist at further-out levels of the hierarchy. So, for example, if Ctype2 is the first
Cache Type field with a value of 0b000, the value of Ctype3 must be ignored.
Ctype2, [5:3]
Indicates the type of cache if the processor implements L2 cache:
0b000 L2 cache not implemented.
0b100 Unified instruction and data caches at L2.
Ctype1, [2:0]
Indicates the type of cache implemented at L1:
0b011 Separate instruction and data caches at L1.
To access the CLIDR_EL1:
MRS <Xt>, CLIDR_EL1 ; Read CLIDR_EL1 into Xt
Register access is encoded as follows:
Table B2-23 CLIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 0000 0000 001
B2 AArch64 system registers
B2.30 Cache Level ID Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-401
Non-Confidential
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