ARM Cortex-A35 User Manual

1 With ECC.
This field is RO.
SCU-L2 Cache Protection, [21]
SCU-L2 Cache Protection. L2 cache is implemented:
0 Without ECC.
1 With ECC.
This field is RO.
[20:6]
Reserved, RAZ.
L2 Data RAM input latency, [5]
L2 data RAM input latency
0 1-cycle input delay from L2 data RAMs.
1 2-cycle input delay from L2 data RAMs.
This field is RO.
[4:1]
Reserved, RAZ.
L2 Data RAM output latency, [0]
L2 data RAM output latency:
0 2-cycle output delay from L2 data RAMs.
1 3-cycle output delay from L2 data RAMs.
This field is RO.
To access the L2CTLR:
MRC p15, 1, <Rt>, c9, c0, 2; Read L2CTLR into Rt
Register access is encoded as follows:
Table B1-73 L2CTLR access encoding
coproc opc1 CRn CRm opc2
1111 001 1001 0000 010
B1 AArch32 system registers
B1.92 L2 Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-304
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English