SynchPrim, [15:12]
Indicates the implemented Synchronization Primitive instructions.
0x2 • The LDREX and STREX instructions.
• The CLREX, LDREXB, STREXB, and STREXH instructions.
• The LDREXD and STREXD instructions.
SVC, [11:8]
Indicates the implemented SVC instructions:
0x1 The SVC instruction.
SIMD, [7:4]
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
0x3 • The SSAT and USAT instructions, and the Q bit in the PSRs.
• The PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8,
SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16,
SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX,
UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX,
USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and
the GE[3:0] bits in the PSRs.
Saturate, [3:0]
Indicates the implemented Saturate instructions:
0x1 The QADD, QDADD, QDSUB, QSUB and the Q bit in the PSRs.
To access the ID_ISAR3:
MRC p15, 0, <Rt>, c0, c2, 3 ; Read ID_ISAR3 into Rt
Register access is encoded as follows:
Table B1-60 ID_ISAR3 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 011
B1 AArch32 system registers
B1.77 Instruction Set Attribute Register 3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-276
Non-Confidential
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