ARM Cortex-A35 User Manual

• If two or more first memory error events from different RAMs occur in the same cycle, one of the
errors is selected arbitrarily, while the Other error count field is incremented only by one.
• If two or more memory error events from different RAMs, that do not match the RAMID, bank, way,
or index information in this register while the sticky Valid bit is set, occur in the same cycle, the
Other error count field is incremented only by one.
To access the L2MERRSR_EL1:
MRS <Xt>, S3_1_C15_C2_3 ; Read L2MERRSR_EL1 into Xt
MSR S3_1_C15_C2_3, <Xt> ; Write Xt into L2MERRSR_EL1
Register access is encoded as follows:
Table B2-67 L2MERRSR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 1111 0010 011
B2 AArch64 system registers
B2.76 L2 Memory Error Syndrome Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-495
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English