Chapter B2
AArch64 system registers
This chapter describes the system registers in the AArch64 state.
It contains the following sections:
• B2.1 AArch64 register summary on page B2-362.
• B2.2 AArch64 Identification registers on page B2-363.
• B2.3 AArch64 Exception handling registers on page B2-365.
• B2.4 AArch64 Virtual memory control registers on page B2-366.
• B2.5 AArch64 Other System control registers on page B2-368.
• B2.6 AArch64 Cache maintenance operations on page B2-369.
• B2.7 AArch64 TLB maintenance operations on page B2-370.
• B2.8 AArch64 Address translation operations on page B2-371.
• B2.9 AArch64 Miscellaneous operations on page B2-372.
• B2.10 AArch64 Performance monitor registers on page B2-373.
• B2.11 AArch64 Reset registers on page B2-375.
• B2.12 AArch64 Secure registers on page B2-376.
• B2.13 AArch64 Virtualization registers on page B2-377.
• B2.14 AArch64 EL2 TLB maintenance operations on page B2-379.
• B2.15 AArch64 GIC system registers on page B2-380.
• B2.16 AArch64 Generic Timer registers on page B2-382.
• B2.17 AArch64 Thread registers on page B2-383.
• B2.18 AArch64 Implementation defined registers on page B2-384.
• B2.19 Auxiliary Control Register, EL1 on page B2-386.
• B2.20 Auxiliary Control Register, EL2 on page B2-387.
• B2.21 Auxiliary Control Register, EL3 on page B2-389.
• B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391.
• B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392.
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