• B2.24 Auxiliary ID Register, EL1 on page B2-393.
• B2.25 Auxiliary Memory Attribute Indirection Register, EL1 on page B2-394.
• B2.26 Auxiliary Memory Attribute Indirection Register, EL2 on page B2-395.
• B2.27 Auxiliary Memory Attribute Indirection Register, EL3 on page B2-396.
• B2.28 Configuration Base Address Register, EL1 on page B2-397.
• B2.29 Cache Size ID Register, EL1 on page B2-398.
• B2.30 Cache Level ID Register, EL1 on page B2-400.
• B2.31 Architectural Feature Access Control Register, EL1 on page B2-402.
• B2.32 Architectural Feature Trap Register, EL2 on page B2-404.
• B2.33 Architectural Feature Trap Register, EL3 on page B2-406.
• B2.34 Cache Size Selection Register, EL1 on page B2-408.
• B2.35 Cache Type Register, EL0 on page B2-410.
• B2.36 CPU Auxiliary Control Register, EL1 on page B2-412.
• B2.37 CPU Extended Control Register, EL1 on page B2-416.
• B2.38 CPU Memory Error Syndrome Register, EL1 on page B2-418.
• B2.39 Domain Access Control Register, EL2 on page B2-421.
• B2.40 Data Cache Zero ID Register, EL0 on page B2-422.
• B2.41 Exception Syndrome Register, EL1 on page B2-423.
• B2.42 Exception Syndrome Register, EL2 on page B2-425.
• B2.43 Exception Syndrome Register, EL3 on page B2-427.
• B2.44 Fault Address Register, EL1 on page B2-429.
• B2.45 Fault Address Register, EL2 on page B2-430.
• B2.46 Fault Address Register, EL3 on page B2-431.
• B2.47 Hyp Auxiliary Configuration Register, EL2 on page B2-432.
• B2.48 Hypervisor Configuration Register, EL2 on page B2-433.
• B2.49 Hypervisor IPA Fault Address Register, EL2 on page B2-440.
• B2.50 Hyp System Trap Register, EL2 on page B2-441.
• B2.51 AArch64 Debug Feature Register 0, EL1 on page B2-444.
• B2.52 AArch64 Instruction Set Attribute Register 0, EL1 on page B2-446.
• B2.53 AArch64 Memory Model Feature Register 0, EL1 on page B2-448.
• B2.54 AArch64 Processor Feature Register 0, EL1 on page B2-450.
• B2.55 AArch32 Auxiliary Feature Register 0, EL1 on page B2-452.
• B2.56 AArch32 Debug Feature Register 0, EL1 on page B2-453.
• B2.57 AArch32 Instruction Set Attribute Register 0, EL1 on page B2-455.
• B2.58 AArch32 Instruction Set Attribute Register 1, EL1 on page B2-457.
• B2.59 AArch32 Instruction Set Attribute Register 2, EL1 on page B2-459.
• B2.60 AArch32 Instruction Set Attribute Register 3, EL1 on page B2-461.
• B2.61 AArch32 Instruction Set Attribute Register 4, EL1 on page B2-463.
• B2.62 AArch32 Instruction Set Attribute Register 5, EL1 on page B2-465.
• B2.63 AArch32 Memory Model Feature Register 0, EL1 on page B2-467.
• B2.64 AArch32 Memory Model Feature Register 1, EL1 on page B2-469.
• B2.65 AArch32 Memory Model Feature Register 2, EL1 on page B2-471.
• B2.66 AArch32 Memory Model Feature Register 3, EL1 on page B2-473.
• B2.67 AArch32 Processor Feature Register 0, EL1 on page B2-475.
• B2.68 AArch32 Processor Feature Register 1, EL1 on page B2-477.
• B2.69 Instruction Fault Status Register, EL2 on page B2-479.
• B2.70 IFSR32_EL2 with Short-descriptor translation table format on page B2-480.
• B2.71 IFSR32_EL2 with Long-descriptor translation table format on page B2-482.
• B2.72 Interrupt Status Register, EL1 on page B2-484.
• B2.73 L2 Auxiliary Control Register, EL1 on page B2-486.
• B2.74 L2 Control Register, EL1 on page B2-489.
• B2.75 L2 Extended Control Register, EL1 on page B2-491.
• B2.76 L2 Memory Error Syndrome Register, EL1 on page B2-493.
• B2.77 Memory Attribute Indirection Register, EL1 on page B2-496.
• B2.78 Memory Attribute Indirection Register, EL2 on page B2-498.
• B2.79 Memory Attribute Indirection Register, EL3 on page B2-499.
B2 AArch64 system registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-360
Non-Confidential
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