• B2.80 Monitor Debug Configuration Register, EL2 on page B2-500.
• B2.81 Monitor Debug Configuration Register, EL3 on page B2-503.
• B2.82 Monitor Debug System Control Register, EL1 on page B2-506.
• B2.83 Main ID Register, EL1 on page B2-510.
• B2.84 Multiprocessor Affinity Register, EL1 on page B2-512.
• B2.85 Physical Address Register, EL1 on page B2-514.
• B2.86 Revision ID Register, EL1 on page B2-518.
• B2.87 Reset Management Register, EL3 on page B2-519.
• B2.88 Reset Vector Base Address Register, EL3 on page B2-521.
• B2.89 Secure Configuration Register, EL3 on page B2-522.
• B2.90 System Control Register, EL1 on page B2-525.
• B2.91 System Control Register, EL2 on page B2-529.
• B2.92 System Control Register, EL3 on page B2-532.
• B2.93 Secure Debug Enable Register, EL3 on page B2-535.
• B2.94 Translation Control Register, EL1 on page B2-536.
• B2.95 Translation Control Register, EL2 on page B2-540.
• B2.96 Translation Control Register, EL3 on page B2-543.
• B2.97 Translation Table Base Register 0, EL1 on page B2-546.
• B2.98 Translation Table Base Register 1, EL1 on page B2-548.
• B2.99 Translation Table Base Register 0, EL3 on page B2-550.
• B2.100 Vector Base Address Register, EL1 on page B2-551.
• B2.101 Vector Base Address Register, EL2 on page B2-552.
• B2.102 Vector Base Address Register, EL3 on page B2-553.
• B2.103 Virtualization Multiprocessor ID Register, EL2 on page B2-554.
• B2.104 Virtualization Processor ID Register, EL2 on page B2-555.
• B2.105 Virtualization Translation Control Register, EL2 on page B2-556.
B2 AArch64 system registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-361
Non-Confidential
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