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ARM Cortex-A35 User Manual

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TID2, [17]
Trap ID Group 2. When 1, this causes reads (or writes to CSSELR) to the following registers
executed from EL1 or EL0 if not UNDEFINED to be trapped to EL2:
CTR, CCSIDR, CLIDR, and CSSELR.
The reset value is 0.
TID1, [16]
Trap ID Group 1. When 1, this causes reads to the following registers executed from EL1 to be
trapped to EL2:
TCMTR, TLBTR, AIDR, and REVIDR.
The reset value is 0.
TID0, [15]
Trap ID Group 0. When 1, this causes reads to the following registers executed from EL1 or
EL0 if not UNDEFINED to be trapped to EL2:
FPSID and JIDR.
The reset value is 0.
TWE, [14]
Trap WFE. When 1, this causes the WFE instruction executed from EL1 or EL0 to be trapped to
EL2 if the instruction would otherwise cause suspension of execution. For example, if the event
register is not set:
The reset value is 0.
TWI, [13]
Trap WFI. When 1, this causes the WFI instruction executed from EL1 or EL0 to be trapped to
EL2 if the instruction would otherwise cause suspension of execution. For example, if there is
not a pending WFI wake-up event:
The reset value is 0.
DC, [12]
Default cacheable. When this bit is set to 1, and the Non-secure EL1 and EL0 stage 1 MMU is
disabled, the memory type and attributes determined by the stage 1 translation is Normal, Non-
shareable, Inner Write-Back Write-Allocate, Outer Write-Back Write-Allocate.
The reset value is 0.
BSU, [11:10]
Barrier Shareability upgrade. The value in this field determines the minimum shareability
domain that is applied to any barrier executed from EL1 or EL0. The possible values are:
0b00 No effect.
0b01 Inner Shareable.
0b10 Outer Shareable.
0b11 Full System.
The reset value is 0.
B1 AArch32 system registers
B1.61 Hyp Configuration Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-243
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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