ARM Cortex-A35 User Manual

FB, [9]
Force broadcast. When 1, this causes the following instructions to be broadcast within the Inner
Shareable domain when executed from Non-secure EL1:
TLBIALL, TLBIMVA, TLBIASID, TLBIMVAA, BPIALL, and ICIALLU.
The reset value is 0.
VA, [8]
Virtual Asynchronous Abort exception. When the AMO bit is set to 1, setting this bit signals a
virtual Asynchronous Abort exception to the Guest OS, when the processor is executing in Non-
secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the corresponding physical
exception.
The reset value is 0.
VI, [7]
Virtual IRQ exception. When the IMO bit is set to 1, setting this bit signals a virtual IRQ
exception to the Guest OS, when the processor is executing in Non-secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the corresponding physical
exception.
The reset value is 0.
VF, [6]
Virtual FIQ exception. When the FMO bit is set to 1, setting this bit signals a virtual FIQ
exception to the Guest OS, when the processor is executing in Non-secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the corresponding physical
exception.
The reset value is 0.
AMO, [5]
Asynchronous Abort Mask Override. When this is set to 1, it overrides the effect of CPSR.A,
and enables virtual exception signaling by the VA bit.
The reset value is 0.
IMO, [4]
IRQ Mask Override. When this is set to 1, it overrides the effect of CPSR.I, and enables virtual
exception signaling by the VI bit.
The reset value is 0.
FMO, [3]
FIQ Mask Override. When this is set to 1, it overrides the effect of CPSR.F, and enables virtual
exception signaling by the VF bit.
The reset value is 0.
PTW, [2]
Protected Table Walk. When 1, if the stage 2 translation of a translation table access made as
part of a stage 1 translation table walk at EL0 or EL1 maps that translation table access to
Device memory, the access is faulted as a stage 2 Permission fault.
The reset value is 0.
B1 AArch32 system registers
B1.61 Hyp Configuration Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English