ARM Cortex-A35

0x6 The processor implements Armv8 Debug architecture.
DEVID_imp, [15]
Reserved, RAO.
nSUHD_imp, [14]
Secure User Halting Debug not implemented bit. The value is:
1 The processor does not implement Secure User Halting Debug.
PCSR_imp, [13]
Reserved, RAZ.
SE, [12]
EL3 implemented. The value is:
1 The processor implements EL3.
[11:0]
Reserved, RES0.
To access the DBGDIDR:
MRC p14, 0, <Rt>, c0, c0, 0; Read Debug ID Register
C6 AArch32 debug registers
C6.4 Debug ID Register
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