Table B2-1 AArch64 identification registers (continued)
Name Type Reset Width Description
ID_AA64DFR1_EL1 RO
0x00000000
64 AArch64 Debug Feature Register 1
ID_AA64AFR0_EL1 RO
0x00000000
64 AArch64 Auxiliary Feature Register 0
ID_AA64AFR1_EL1 RO
0x00000000
64 AArch64 Auxiliary Feature Register 1
ID_AA64ISAR0_EL1 RO
0x00011120
64
B2.52 AArch64 Instruction Set Attribute Register 0, EL1 on page B2-446
ID_AA64ISAR0_EL1 has the value 0x00010000 if the Cryptographic
Extension is not implemented and enabled.
ID_AA64ISAR1_EL1 RO
0x00000000
64 AArch64 Instruction Set Attribute Register 1
ID_AA64MMFR0_EL1 RO
0x00101122
64 B2.53 AArch64 Memory Model Feature Register 0, EL1 on page B2-448
ID_AA64MMFR1_EL1 RO
0x00000000
64 AArch64 Memory Model Feature Register 1
CCSIDR_EL1 RO - 32
B2.29 Cache Size ID Register, EL1 on page B2-398
The reset value depends on the implementation. See the register description
for details.
CLIDR_EL1 RO
0x0A400023
64
B2.30 Cache Level ID Register, EL1 on page B2-400
The reset value is 0x09200003 if the L2 cache is not implemented.
The reset value is 0x0A200023 if the L2 cache is implemented and
BROADCASTINNER is set to 0.
The reset value is 0x0A400023 if the L2 cache is implemented and
BROADCASTINNER is set to 1.
AIDR_EL1 RO
0x00000000
32 B2.24 Auxiliary ID Register, EL1 on page B2-393
CSSELR_EL1 RW
0x00000000
32 B2.34 Cache Size Selection Register, EL1 on page B2-408
CTR_EL0 RO
0x84448004
32 B2.35 Cache Type Register, EL0 on page B2-410
DCZID_EL0 RO
0x00000004
32 B2.40 Data Cache Zero ID Register, EL0 on page B2-422
VPIDR_EL2 RW
0x411FD040
32 B2.104 Virtualization Processor ID Register, EL2 on page B2-555
VMPIDR_EL2 RO - 64
B2.103 Virtualization Multiprocessor ID Register, EL2 on page B2-554
The reset value is the value of the Multiprocessor Affinity Register.
B2 AArch64 system registers
B2.2 AArch64 Identification registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-364
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