ARM Cortex-A35

Indicates the implemented combined Compare and Branch instructions in the T32 instruction
set:
0x1 CBNZ and CBZ.
Bitfield, [11:8]
Indicates the implemented bit field instructions:
0x1 BFC, BFI, SBFX, and UBFX.
BitCount, [7:4]
Indicates the implemented Bit Counting instructions:
0x1 CLZ.
Swap, [3:0]
Indicates the implemented Swap instructions in the A32 instruction set:
0x0 None implemented.
To access the ID_ISAR0:
MRC p15, 0, <Rt>, c0, c2, 0 ; Read ID_ISAR0 into Rt
Register access is encoded as follows:
Table B1-57 ID_ISAR0 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 000
B1 AArch32 system registers
B1.74 Instruction Set Attribute Register 0
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B1-270
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