EasyManuals Logo

ARM Cortex-A35 User Manual

Default Icon
894 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #154 background imageLoading...
Page #154 background image
Table B1-2 c0 register summary (continued)
Op1 CRm Op2 Name Reset Description
1 c0 0 CCSIDR -
B1.39 Cache Size ID Register on page B1-201
1 CLIDR
0x0A200023
B1.40 Cache Level ID Register on page B1-204
The value is 0x09200003 if the L2 cache is not implemented.
7 AIDR
0x00000000
B1.34 Auxiliary ID Register on page B1-196
2 c0 0 CSSELR
0x00000000
B1.45 Cache Size Selection Register on page B1-217
4 c0 0 VPIDR
0x411FD040
B1.121 Virtualization Processor ID Register on page B1-356
5 VMPIDR -
B1.120 Virtualization Multiprocessor ID Register on page B1-355
The reset value is the value of the Multiprocessor Affinity Register.
B1 AArch32 system registers
B1.2 c0 registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-154
Non-Confidential

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM Cortex-A35 and is the answer not in the manual?

ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

Related product manuals