L2 cache data RAM error injection enable. The possible values are:
0 Normal behavior, errors are not injected. This is the reset value.
1 Double-bit errors are injected on all writes to the L2 cache data RAMs.
[28:25]
Reserved, RES0.
L2TEIEN, [24]
L2 cache tag RAM error injection enable. The possible values are:
0 Normal behavior, errors are not injected. This is the reset value.
1 Double-bit errors are injected on all writes to the L2 cache tag RAMs.
[23:15]
Reserved, RES0.
Enable UniqueClean evictions with data, [14]
Enables sending of WriteEvict transactions for UniqueClean evictions with data.
WriteEvict transactions update downstream caches that are outside the cluster. Enable
WriteEvict transactions only if there is an L3 or system cache implemented in the system.
The possible values are:
0 Disables UniqueClean evictions with data. This is the reset value for ACE.
1 Enables UniqueClean evictions with data. This is the reset value for CHI.
In AXI implementations, this field is RES0.
Some ACE interconnects might not support the WriteEvict transaction. You must not enable this
bit if your interconnect does not support WriteEvict transactions.
[13:4]
Reserved, RES0.
Disable clean/evict push to external, [3]
Disables sending of Evict transactions for clean cache lines that are evicted from the processor.
This is required only if the external interconnect contains a snoop filter that requires notification
when the processor evicts the cache line. The possible values are:
0 Enables clean/evict to be pushed out to external. This is the reset value for ACE.
1 Disables clean/evict from being pushed to external. This is the reset value for CHI.
In AXI implementations, this field is RES1.
[2:0]
Reserved, RES0.
To access the L2ACTLR_EL1:
MRS Rt, S3_1_C15_C0_0; Read L2ACTLR_EL1 into Rt
MSR S3_1_C15_C0_0, Rt; Write Rt to L2ACTLR_EL1
Register access is encoded as follows:
B2 AArch64 system registers
B2.73 L2 Auxiliary Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-487
Non-Confidential
To Next Page
Loading...
Need help?
General
