ARM Cortex-A35

0x2 AESE, AESD, AESMC and AESIMC, plus PMULL and PMULL2 instructions operating on 64-
bit data.
SEVL, [3:0]
Indicates whether the SEVL instruction is implemented:
0x1 SEVL implemented to send event local.
To access the ID_ISAR5_EL1:
MRS <Xt>, ID_ISAR5_EL1 ; Read ID_ISAR5_EL1 into Xt
Register access is encoded as follows:
Table B2-54 ID_ISAR5_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 101
B2 AArch64 system registers
B2.62 AArch32 Instruction Set Attribute Register 5, EL1
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B2-466
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