WriteBack, [11:8]
Indicates the support for Write-Back addressing modes:
0x1 Processor supports all of the Write-Back addressing modes defined in Armv8.
WithShifts, [7:4]
Indicates the support for instructions with shifts.
0x4 • Support for shifts of loads and stores over the range LSL 0-3.
• Support for other constant shift options, both on load/store and other instructions.
• Support for register-controlled shift options.
Unpriv, [3:0]
Indicates the implemented unprivileged instructions.
0x2 • The LDRBT, LDRT, STRBT, and STRT instructions.
• The LDRHT, LDRSBT, LDRSHT, and STRHT instructions.
To access the ID_ISAR4_EL1:
MRS <Xt>, ID_ISAR4_EL1 ; Read ID_ISAR4_EL1 into Xt
Register access is encoded as follows:
Table B2-53 ID_ISAR4_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 100
B2 AArch64 system registers
B2.61 AArch32 Instruction Set Attribute Register 4, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-464
Non-Confidential
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