ARM Cortex-A35 User Manual

Translation table walk disable for translations using TTBR1. This bit controls whether a
translation table walk is performed on a TLB miss, for an address that is translated using
TTBR1:
0
Perform translation table walks using TTBR1.
1
A TLB miss on an address that is translated using TTBR1 generates a Translation fault.
No translation table walk is performed.
A1, [22]
Selects whether TTBR0 or TTBR1 defines the ASID:
0 TTBR0.ASID defines the ASID.
1 TTBR1.ASID defines the ASID.
[21:19]
Reserved, RES0.
T1SZ, [18:16]
The size offset of the memory region addressed by TTBR1. The region size is 2
32-T1SZ
bytes.
Resets to 0.
[15:14]
Reserved, RES0.
SH0, [13:12]
Shareability attribute for memory associated with translation table walks using TTBR0:
0b00 Non-shareable.
0b10 Outer Shareable.
0b11 Inner Shareable.
Other values are reserved.
Resets to 0.
ORGN0, [11:10]
Outer cacheability attribute for memory associated with translation table walks using TTBR0:
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
Resets to 0.
IRGN0, [9:8]
Inner cacheability attribute for memory associated with translation table walks using TTBR0:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
Resets to 0.
B1 AArch32 system registers
B1.112 TTBCR with Long-descriptor translation table format
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reserved.
B1-344
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English