EPD0, [7]
Translation table walk disable for translations using TTBR0. This bit controls whether a
translation table walk is performed on a TLB miss, for an address that is translated using
TTBR0:
0 Perform translation table walks using TTBR0.
1 A TLB miss on an address that is translated using TTBR0 generates a Translation
fault. No translation table walk is performed.
[6:3]
Reserved, RES0.
T0SZ, [2:0]
The size offset of the memory region addressed by TTBR0. The region size is 2
32-T0SZ
bytes.
Resets to 0.
To access the TTBCR:
MRC p15,0,<Rt>,c2,c0,0 ; Read TTBR0 into Rt
MCR p15,0,<Rt>,c2,c0,0 ; Write Rt to TTBR0
Register access is encoded as follows:
Table B1-93 TTBCR access encoding
coproc opc1 CRn CRm opc2
1111 000 0010 0000 010
B1 AArch32 system registers
B1.112 TTBCR with Long-descriptor translation table format
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-345
Non-Confidential
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