ARM Cortex-A35 User Manual

[14]
Reserved, RES0.
T13, [13]
Trap coprocessor primary register CRn = 13. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 13 to Hyp
mode.
The reset value is 0.
T12, [12]
Trap coprocessor primary register CRn = 12. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 12 to Hyp
mode.
The reset value is 0.
T11, [11]
Trap coprocessor primary register CRn = 11. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 11 to Hyp
mode.
The reset value is 0.
T10, [10]
Trap coprocessor primary register CRn = 10. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 10 to Hyp
mode.
The reset value is 0.
T9, [9]
Trap coprocessor primary register CRn = 9. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 9 to Hyp mode.
The reset value is 0.
T8, [8]
Trap coprocessor primary register CRn = 8. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 8 to Hyp mode.
The reset value is 0.
T7, [7]
Trap coprocessor primary register CRn = 7. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
B1 AArch32 system registers
B1.69 Hyp System Trap Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English