ARM Cortex-A35 User Manual

The reset value is 0.
T5, [5]
Trap coprocessor primary register CRn = 5. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 5 to Hyp mode.
The reset value is 0.
[4]
Reserved, RES0.
T3, [3]
Trap coprocessor primary register CRn = 3. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 3 to Hyp mode.
The reset value is 0.
T2, [2]
Trap coprocessor primary register CRn = 2. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 2 to Hyp mode.
The reset value is 0.
T1, [1]
Trap coprocessor primary register CRn = 1. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 1 to Hyp mode.
The reset value is 0.
T0, [0]
Trap coprocessor primary register CRn = 0. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 0 to Hyp mode.
The reset value is 0.
To access the HSTR_EL2:
MRS <Xt>, HSTR_EL2 ; Read HSTR_EL2 into Xt
MSR HSTR_EL2, <Xt> ; Write Xt to HSTR_EL2
Register access is encoded as follows:
Table B2-43 HSTR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 0001 0001 011
B2 AArch64 system registers
B2.50 Hyp System Trap Register, EL2
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B2-443
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English