1 Disable optimized Data Memory Barrier behavior.
[9:7]
Reserved, RES0.
L1DEIEN, [6]
L1 D-cache data RAM error injection enable. The possible values are:
0 Normal behavior, errors are not injected. This is the reset value.
1 Double-bit errors are injected on all writes to the L1 D-cache data RAMs for the first
word of each 32-byte region.
[5:0]
Reserved, RES0.
To access the CPUACTLR_EL1:
MRS <Xt>, S3_1_C15_C2_0 ; Read EL1 CPU Auxiliary Control Register
MSR S3_1_C15_C2_0, <Xt> ; Write EL1 CPU Auxiliary Control Register
Register access is encoded as follows:
Table B2-27 CPUACTLR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 1111 0010 000
B2 AArch64 system registers
B2.36 CPU Auxiliary Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-415
Non-Confidential
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