ARM Cortex-A35 User Manual

0b100 64 Architectural Timer ticks are required before retention entry.
0b101 128 Architectural Timer ticks are required before retention entry.
0b110 256 Architectural Timer ticks are required before retention entry.
0b111 512 Architectural Timer ticks are required before retention entry.
This field is present only if the Advanced SIMD and floating-point support is implemented.
Otherwise, it is RES0.
[2:0]
CPU retention control. The possible values are:
0b000 Disable the retention circuit. This is the reset value.
0b001 2 Architectural Timer ticks are required before retention entry.
0b010 8 Architectural Timer ticks are required before retention entry.
0b011 32 Architectural Timer ticks are required before retention entry.
0b100 64 Architectural Timer ticks are required before retention entry.
0b101 128 Architectural Timer ticks are required before retention entry.
0b110 256 Architectural Timer ticks are required before retention entry.
0b111 512 Architectural Timer ticks are required before retention entry.
To access the CPUECTLR_EL1:
MRS <Xt>, S3_1_C15_C2_1; Read EL1 CPU Extended Control Register
MSR S3_1_C15_C2_1, <Xt>; Write EL1 CPU Extended Control Register
Register access is encoded as follows:
Table B2-28 CPUECTLR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 1111 0010 001
B2 AArch64 system registers
B2.37 CPU Extended Control Register, EL1
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B2-417
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English