ARM Cortex-A35 User Manual

Table B1-69 Encodings of LL bits associated with the MMU fault
Bits Meaning
0b00
Reserved
0b01
Level 1
0b10
Level 2
0b11
Level 3
If a Data Abort exception is generated by an instruction cache maintenance operation when the Long-
descriptor translation table format is selected, the fault is reported as a Cache Maintenance fault in the
DFSR or HSR with the appropriate Fault Status code. For such exceptions reported in the DFSR, the
corresponding IFSR is UNKNOWN.
To access the IFSR:
MRC p15, 0, <Rt>, c5, c0, 1; Read IFSR into Rt
MCR p15, 0, <Rt>, c5, c0, 1; Write Rt to IFSR
Register access is encoded as follows:
Table B1-70 IFSR access encoding
coproc opc1 CRn CRm opc2
1111 000 0101 0000 001
B1 AArch32 system registers
B1.89 IFSR with Long-descriptor translation table format
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B1-298
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English