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ARM Cortex-A35 User Manual

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B1.80 Memory Model Feature Register 0 on page B1-281.
B1.81 Memory Model Feature Register 1 on page B1-283.
B1.82 Memory Model Feature Register 2 on page B1-285.
B1.83 Memory Model Feature Register 3 on page B1-287.
B1.84 Processor Feature Register 0 on page B1-289.
B1.85 Processor Feature Register 1 on page B1-291.
B1.86 Instruction Fault Address Register on page B1-293.
B1.87 Instruction Fault Status Register on page B1-294.
B1.88 IFSR with Short-descriptor translation table format on page B1-295.
B1.89 IFSR with Long-descriptor translation table format on page B1-297.
B1.90 Interrupt Status Register on page B1-299.
B1.91 L2 Auxiliary Control Register on page B1-301.
B1.92 L2 Control Register on page B1-303.
B1.93 L2 Extended Control Register on page B1-305.
B1.94 L2 Memory Error Syndrome Register on page B1-307.
B1.95 Memory Attribute Indirection Registers 0 and 1 on page B1-310.
B1.96 Main ID Register on page B1-313.
B1.97 Multiprocessor Affinity Register on page B1-315.
B1.98 Non-Secure Access Control Register on page B1-317.
B1.99 Normal Memory Remap Register on page B1-319.
B1.100 Physical Address Register on page B1-321.
B1.101 Primary Region Remap Register on page B1-322.
B1.102 Revision ID Register on page B1-325.
B1.103 Reset Management Register on page B1-326.
B1.104 Secure Configuration Register on page B1-328.
B1.105 System Control Register on page B1-331.
B1.106 Secure Debug Control Register on page B1-335.
B1.107 Secure Debug Enable Register on page B1-337.
B1.108 TCM Type Register on page B1-339.
B1.109 TLB Type Register on page B1-340.
B1.110 Translation Table Base Control Register on page B1-341.
B1.111 TTBCR with Short-descriptor translation table format on page B1-342.
B1.112 TTBCR with Long-descriptor translation table format on page B1-343.
B1.113 Translation Table Base Register 0 on page B1-346.
B1.114 TTBR0 with Short-descriptor translation table format on page B1-347.
B1.115 TTBR0 with Long-descriptor translation table format on page B1-349.
B1.116 Translation Table Base Register 1 on page B1-350.
B1.117 TTBR1 with Short-descriptor translation table format on page B1-351.
B1.118 TTBR1 with Long-descriptor translation table format on page B1-353.
B1.119 Vector Base Address Register on page B1-354.
B1.120 Virtualization Multiprocessor ID Register on page B1-355.
B1.121 Virtualization Processor ID Register on page B1-356.
B1.122 Virtualization Translation Control Register on page B1-357.
B1 AArch32 system registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-149
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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