ARM Cortex-A35 User Manual

• B1.24 AArch32 Address registers on page B1-181.
• B1.25 AArch32 Thread registers on page B1-182.
• B1.26 AArch32 Performance monitor registers on page B1-183.
• B1.27 AArch32 Secure registers on page B1-185.
• B1.28 AArch32 Virtualization registers on page B1-186.
• B1.29 AArch32 GIC system registers on page B1-188.
• B1.30 AArch32 Generic Timer registers on page B1-190.
• B1.31 AArch32 Implementation defined registers on page B1-191.
• B1.32 Auxiliary Control Register on page B1-193.
• B1.33 Auxiliary Data Fault Status Register on page B1-195.
• B1.34 Auxiliary ID Register on page B1-196.
• B1.35 Auxiliary Instruction Fault Status Register on page B1-197.
• B1.36 Auxiliary Memory Attribute Indirection Register 0 on page B1-198.
• B1.37 Auxiliary Memory Attribute Indirection Register 1 on page B1-199.
• B1.38 Configuration Base Address Register on page B1-200.
• B1.39 Cache Size ID Register on page B1-201.
• B1.40 Cache Level ID Register on page B1-204.
• B1.41 Architectural Feature Access Control Register on page B1-206.
• B1.42 CPU Auxiliary Control Register on page B1-208.
• B1.43 CPU Extended Control Register on page B1-212.
• B1.44 CPU Memory Error Syndrome Register on page B1-214.
• B1.45 Cache Size Selection Register on page B1-217.
• B1.46 Cache Type Register on page B1-219.
• B1.47 Domain Access Control Register on page B1-221.
• B1.48 Data Fault Address Register on page B1-222.
• B1.49 Data Fault Status Register on page B1-223.
• B1.50 DFSR with Short-descriptor translation table format on page B1-224.
• B1.51 DFSR with Long-descriptor translation table format on page B1-226.
• B1.52 Encoding of ISS[24:20] when HSR[31:30] is 0b00 on page B1-228.
• B1.53 FCSE Process ID Register on page B1-229.
• B1.54 Hyp Auxiliary Configuration Register on page B1-230.
• B1.55 Hyp Auxiliary Control Register on page B1-231.
• B1.56 Hyp Auxiliary Data Fault Status Syndrome Register on page B1-233.
• B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register on page B1-234.
• B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0 on page B1-235.
• B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1 on page B1-236.
• B1.60 Hyp Architectural Feature Trap Register on page B1-237.
• B1.61 Hyp Configuration Register on page B1-240.
• B1.62 Hyp Configuration Register 2 on page B1-246.
• B1.63 Hyp Debug Control Register on page B1-248.
• B1.64 Hyp Data Fault Address Register on page B1-251.
• B1.65 Hyp Instruction Fault Address Register on page B1-252.
• B1.66 Hyp IPA Fault Address Register on page B1-253.
• B1.67 Hyp System Control Register on page B1-254.
• B1.68 Hyp Syndrome Register on page B1-258.
• B1.69 Hyp System Trap Register on page B1-259.
• B1.70 Hyp Translation Control Register on page B1-263.
• B1.71 Hyp Vector Base Address Register on page B1-265.
• B1.72 Auxiliary Feature Register 0 on page B1-266.
• B1.73 Debug Feature Register 0 on page B1-267.
• B1.74 Instruction Set Attribute Register 0 on page B1-269.
• B1.75 Instruction Set Attribute Register 1 on page B1-271.
• B1.76 Instruction Set Attribute Register 2 on page B1-273.
• B1.77 Instruction Set Attribute Register 3 on page B1-275.
• B1.78 Instruction Set Attribute Register 4 on page B1-277.
• B1.79 Instruction Set Attribute Register 5 on page B1-279.
B1 AArch32 system registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
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B1-148
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English