ARM Cortex-A35 User Manual

Table C5-10 TLB encoding for memory types and shareability (continued)
Bits Memory type Description
[6]
Device
Non-coherent, Outer WB
0
Non-coherent, Outer NC
Non-coherent, Outer WT
1
Coherent, Inner WB and Outer WB
Transience:
0
Non-transient
1
Transient.
[5:4]
Device Stage 1 (Non-device) overridden by stage 2 (Device)
00
Not overridden
01
Overridden.
Non-coherent, Outer WB
Inner type:
10
NC.
11
WT.
Non-coherent, Outer NC
11
Non-coherent, Outer WT
Inner type:
00
NC.
01
WB.
10
WT.
Coherent, Inner WB and Outer WB
Inner allocation hint:
00
NA.
01
WA.
10
RA.
11
WRA.
C5 Direct access to internal memory
C5.4 Encoding for the main TLB RAM
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C5-615
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English