ARM Cortex-A35 User Manual

Table C5-9 Main TLB descriptor data fields (continued)
Bits Name Description
[57:55]
Size This field shows the encoding for the combined page size for stage 1 and stage 2.
VMSAv8-32 Short-descriptor translation table format:
0b000
4KB.
0b010
64KB.
0b100
1MB.
0b110
16MB.
In the VMSAv8-32 Long-descriptor translation table format and the VMSAv8-64 translation
table format, domain[1] is used in conjunction with Size, {domain[1], Size}:
0b0001
4KB.
0b1001
16KB.
0b0011
64KB.
0b0101
2MB.
0b1011
32MB.
0b0111
512MB.
[54:39] ASID Address Space Identifier.
[38:31] VMID Virtual Machine Identifier.
[30] NS (walk) Security state that the entry was fetched in.
[29:2] VA Virtual Address.
[1] Address Sign bit VA[48] sign bit.
[0] Valid
Valid bit:
0
Entry does not contain valid data.
1
Entry contains valid data.
The following table shows the main TLB memory types and shareability.
Table C5-10 TLB encoding for memory types and shareability
Bits Memory type Description
[7]
Device
Non-coherent, Outer WB
Non-coherent, Outer NC
Non-coherent, Outer WT
0
Coherent, Inner WB and Outer WB 1
C5 Direct access to internal memory
C5.4 Encoding for the main TLB RAM
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C5-614
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English