ARM Cortex-A35 User Manual

Table C5-9 Main TLB descriptor data fields (continued)
Bits Name Description
[110:108]
S1 Size The stage 1 size that gave this translation.
VMSAv8-32 Short-descriptor translation table format:
0b000
4KB.
0b010
64KB.
0b011
1MB.
0b101
16MB.
In the VMSAv8-32 Long-descriptor translation table format and the VMSAv8-64 translation
table format, domain[2] is used in conjunction with S1 Size, {domain[2], S1 size}:
0b0000
4KB.
0b0001
16KB.
0b0010
64KB.
0b0100
2MB.
0b0110
32MB.
0b0111
512MB.
0b1111
1GB.
[107:104] Domain
In VMSAv7 format, indicates one of sixteen memory regions.
In non-VMSAv7 formats:
• Domain[0] stores the contiguous bit information.
• Domain[1] stores the page size MSB for the combined page size.
• Domain[2] stores the page size MSB for the stage 1 page size.
[103:96] Memory Type and
shareability
See TLB encoding for memory types and shareability.
[95] XS2 Stage2 executable permissions.
[94] XS1Nonusr Non user mode executable permissions.
[93] XS1Usr User mode executable permissions.
[92-65] PA Physical Address.
[64] NS, descriptor Security state allocated to memory region.
[63:62] HAP Hypervisor access permissions.
[61:59] AP or HYP Access permissions from stage-1 translation, or select EL2 or flag.
[58] nG Not global.
C5 Direct access to internal memory
C5.4 Encoding for the main TLB RAM
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English