ARM Cortex-A35 User Manual

[11:8]
Reserved, RAZ.
CopSDbg, [7:4]
Indicates support for coprocessor-based Secure debug model:
0x6 Processor supports v8 Debug architecture, with CP14 access.
CopDbg, [3:0]
Indicates support for coprocessor-based debug model:
0x6 Processor supports v8 Debug architecture, with CP14 access.
To access the ID_DFR0:
MRC p15,0,<Rt>,c0,c1,2 ; Read ID_DFR0 into Rt
Register access is encoded as follows:
Table B1-56 ID_DFR0 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 010
B1 AArch32 system registers
B1.73 Debug Feature Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-268
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English