ARM Cortex-A35

To access the CSSELR:
MRC p15, 2, <Rt>, c0, c0, 0; Read CSSELR into Rt
MCR p15, 2, <Rt>, c0, c0, 0; Write Rt to CSSELR
Register access is encoded as follows:
Table B1-39 CSSELR access encoding
coproc opc1 CRn CRm opc2
1111 010 0000 0001 000
B1 AArch32 system registers
B1.45 Cache Size Selection Register
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B1-218
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