0x3 Way 3
0x4-0x7 Unused
L1 D-data RAM
0x0 Bank0
0x1 Bank1
0x2 Bank2
0x3 Bank3
...
0x7 Bank7
[17:12]
Reserved, RES0.
RAM address, [11:0]
Indicates the index address of the first memory error.
• A fatal error results in the RAMID, Way, and RAM address recording the fatal error, even if the
sticky bit is set.
• Only L1 Data data and L1 Data dirty RAMs can signal fatal errors, because all other RAM instances
are protected only by parity.
• If two or more memory errors in the same RAM occur in the same cycle, only one error is reported.
• If two or more first memory error events from different RAMs occur in the same cycle, one of the
errors is selected arbitrarily.
• If two or more memory error events from different RAMs, that do not match the RAMID, Way, and
index information in this register while the sticky Valid bit is set, occur in the same cycle, then the
Other error count field is incremented only by one.
To access the CPUMERRSR_EL1:
MRS <Xt>, S3_1_c15_c2_2 ; Read CPUMERRSR into Xt
MSR S3_1_c15_c2_2, <Xt> ; Write Xt to CPUMERRSR
Register access is encoded as follows:
Table B2-29 CPUMERRSR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 1111 0010 010
B2 AArch64 system registers
B2.38 CPU Memory Error Syndrome Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-420
Non-Confidential
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