Indicates the implemented Extend instructions:
0x2 • The SXTB, SXTH, UXTB, and UXTH instructions.
• The SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH
instructions.
Except_AR, [11:8]
Indicates the implemented A profile exception-handling instructions:
0x1 The SRS and RFE instructions, and the A profile forms of the CPS instruction.
Except, [7:4]
Indicates the implemented exception-handling instructions in the A32 instruction set:
0x1 The LDM (exception return), LDM (user registers), and STM (user registers) instruction
versions.
Endian, [3:0]
Indicates the implemented Endian instructions:
0x1 The SETEND instruction, and the E bit in the PSRs.
To access the ID_ISAR1_EL1:
MRS <Xt>, ID_ISAR1_EL1 ; Read ID_ISAR1_EL1 into Xt
Register access is encoded as follows:
Table B2-50 ID_ISAR1_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 001
B2 AArch64 system registers
B2.58 AArch32 Instruction Set Attribute Register 1, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-458
Non-Confidential
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