0 All counters, including PMCCNTR_EL0, are disabled. This is the reset value.
1 All counters are enabled.
This bit is RW.
In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that
MDCR_EL2.HPMN reserves for EL2 use.
On Warm reset, the field resets to 0.
To access the PMCR_EL0:
MRS <Xt>, PMCR_EL0 ; Read PMCR_EL0 into Xt
MSR PMCR_EL0, <Xt> ; Write Xt to PMCR_EL0
To access the PMCR in AArch32 Execution state, read or write the CP15 registers with:
MRC p15, 0, <Rt>, c9, c12, 0; Read Performance Monitor Control Register
MCR p15, 0, <Rt>, c9, c12, 0; Write Performance Monitor Control Register
The PMCR_EL0 can be accessed through the external debug interface, offset 0xE04.
C10 PMU registers
C10.6 Performance Monitors Control Register, EL0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-706
Non-Confidential
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