ARM Cortex-A35 User Manual

Table C10-5 PMU common events (continued)
Bit Event number Event mnemonic Description
[28]
0x1C
TTBR_WRITE_RETIRED
TTBR write, architecturally executed, condition check pass - write to
translation table base:
0
This event is not implemented.
[27]
0x1B
INST_SPEC
Instruction speculatively executed:
1
This event is implemented.
[26]
0x1A
MEMORY_ERROR
Local memory error:
1
This event is implemented.
[25]
0x19
BUS_ACCESS
Bus access:
1
This event is implemented.
[24]
0x18
L2D_CACHE_WB
L2 Data cache Write-Back:
0
This event is not implemented if the Cortex‑A35 processor has
been configured without an L2 cache.
1
This event is implemented if the Cortex‑A35 processor has
been configured with an L2 cache.
[23]
0x17
L2D_CACHE_REFILL
L2 Data cache refill:
0
This event is not implemented if the Cortex‑A35 processor has
been configured without an L2 cache.
1
This event is implemented if the Cortex‑A35 processor has
been configured with an L2 cache.
[22]
0x16
L2D_CACHE
L2 Data cache access:
0
This event is not implemented if the Cortex‑A35 processor has
been configured without an L2 cache.
1
This event is implemented if the Cortex‑A35 processor has
been configured with an L2 cache.
[21]
0x15
L1D_CACHE_WB
L1 Data cache Write-Back:
1
This event is implemented.
[20]
0x14
L1I_CACHE
L1 Instruction cache access:
1
This event is implemented.
[19]
0x13
MEM_ACCESS
Data memory access:
1
This event is implemented.
[18]
0x12
BR_PRED
Predictable branch speculatively executed:
1
This event is implemented.
C10 PMU registers
C10.7 Performance Monitors Common Event Identification Register 0, EL0
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C10-708
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English