ARM Cortex-A35

To access the MAIR0:
MRC p15, 0, <Rt>, c10, c2, 0 ; Read MAIR0 into Rt
MCR p15, 0, <Rt>, c10, c2, 0 ; Write Rt to MAIR0
Register access is encoded as follows:
Table B1-79 MAIR0 access encoding
coproc opc1 CRn CRm opc2
1111 000 1010 0010 000
To access the MAIR1:
MRC p15, 0, <Rt>, c10, c2, 1 ; Read MAIR1 into Rt
MCR p15, 0, <Rt>, c10, c2, 1 ; Write Rt to MAIR1
Register access is encoded as follows:
Table B1-80 MAIR1 access encoding
coproc opc1 CRn CRm opc2
1111 000 1010 0010 001
B1 AArch32 system registers
B1.95 Memory Attribute Indirection Registers 0 and 1
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