ARM Cortex-A35 User Manual

1 WFE instructions executed in AArch32 or AArch64 from EL2, EL1, or EL0 are trapped to
EL3 if the instruction would otherwise cause suspension of execution, that is if:
• The event register is not set.
• There is not a pending WFE wakeup event.
• The instruction is not trapped at EL2 or EL1.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
TWI, [12]
Traps WFI instructions. The possible values are:
0 WFI instructions are not trapped. This is the reset value.
1 WFI instructions executed in AArch32 or AArch64 from EL2, EL1, or EL0 are trapped to
EL3 if the instruction would otherwise cause suspension of execution, that is if there is not a
pending WFI wakeup event and the instruction is not trapped at EL2 or EL1.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
ST, [11]
Enable Secure EL1 access to CNTPS_TVAL_EL1, CNTS_CTL_EL1, and CNTPS_CVAL_EL1
registers. The possible values are:
0 Registers accessible only in EL3. This is the reset value.
1 Registers accessible in EL3 and EL1 when SCR_EL3.NS is 0.
RW, [10]
Execution state control for lower exception levels. The possible values are:
0 Lower levels are all AArch32. This is the reset value.
1 The next lower level is AArch64.
SIF, [9]
Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction
fetches from Non-secure memory. The possible values are:
0 Secure state instruction fetches from Non-secure memory are permitted. This is the reset
value.
1 Secure state instruction fetches from Non-secure memory are not permitted.
HCE, [8]
Hyp Call enable. This bit enables the use of HVC instructions. The possible values are:
0 The HVC instruction is UNDEFINED at all exception levels. This is the reset value.
1 The HVC instruction is enabled at EL1, EL2 or EL3.
SMD, [7]
SMC instruction disable. The possible values are:
0 The SMC instruction is enabled at EL1, EL2, and EL3. This is the reset value.
1 The SMC instruction is UNDEFINED at all exception levels. At EL1, in the Non-secure state, the
HCR_EL2.TSC bit has priority over this control.
[6]
Reserved, RES0.
B2 AArch64 system registers
B2.89 Secure Configuration Register, EL3
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English