[5:4]
Reserved, RES1.
EA, [3]
External Abort and SError interrupt Routing. This bit controls which mode takes external aborts.
The possible values are:
0 External Aborts and SError Interrupts while executing at exception levels other than EL3 are
not taken in EL3. This is the reset value.
1 External Aborts and SError Interrupts while executing at all exception levels are taken in
EL3.
FIQ, [2]
Physical FIQ Routing. The possible values ares:
0 Physical FIQ while executing at exception levels other than EL3 are not taken in EL3. This is
the reset value.
1 Physical FIQ while executing at all exception levels are taken in EL3.
IRQ, [1]
Physical IRQ Routing. The possible values are:
0 Physical IRQ while executing at exception levels other than EL3 are not taken in EL3.
1 Physical IRQ while executing at all exception levels are taken in EL3.
NS, [0]
Non-secure bit. The possible values are. The possible values are:
0 EL0 and EL1 are in Secure state, memory accesses from those exception levels can access
Secure memory. This is the reset value.
1 EL0 and EL1 are in Non-secure state, memory accesses from those exception levels cannot
access Secure memory.
To access the SCR_EL3:
MRS <Xt>, SCR_EL3 ; Read SCR_EL3 into Xt
MSR SCR_EL3, <Xt> ; Write Xt to SCR_EL3
Register access is encoded as follows:
Table B2-83 SCR_EL3 access encoding
op0 op1 CRn CRm op2
11 110 0001 0001 000
B2 AArch64 system registers
B2.89 Secure Configuration Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-524
Non-Confidential
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