Exception endianness. The value of this bit controls the endianness for explicit data accesses at
EL1. This value also indicates the endianness of the translation table data for translation table
lookups. The possible values of this bit are:
0 Little-endian.
1 Big-endian.
The reset value of this bit is determined by the CFGEND configuration pin.
E0E, [24]
Endianness of explicit data access at EL0. The possible values are:
0 Explicit data accesses at EL0 are little-endian. This is reset value.
1 Explicit data accesses at EL0 are big-endian.
[23:22]
Reserved, RES1.
[21]
Reserved, RES0.
[20]
Reserved, RES1.
WXN, [19]
Write permission implies Execute Never (XN). This bit can be used to require all memory
regions with write permissions to be treated as XN. The possible values are:
0 Regions with write permission are not forced XN. This is the reset value.
1 Regions with write permissions are forced XN.
nTWE, [18]
WFE non-trapping. The possible values are:
0 A WFE instruction executed at EL0, that, if this bit was set to 1, would permit entry to a
low-power state, is trapped to EL1.
1 WFE instructions executed as normal. This is the reset value.
[17]
Reserved, RES0.
nTWI, [16]
WFI non-trapping. The possible values are:
0 A WFI instruction executed at EL0, that, if this bit was set to 1, would permit entry to a
low-power state, is trapped to EL1.
1 WFI instructions executed as normal. This is the reset value.
UCT, [15]
Enables EL0 access to the CTR_EL0 register in AArch64 Execution state. The possible values
are:
0 Disables EL0 access to the CTR_EL0 register. This is the reset value.
1 Enables EL0 access to the CTR_EL0 register.
DZE, [14]
Enables access to the DC ZVA instruction at EL0. The possible values are:
B2 AArch64 system registers
B2.90 System Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-526
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