0 Disables execution access to the DC ZVA instruction at EL0. The instruction is
trapped to EL1. This is the reset value.
1 Enables execution access to the DC ZVA instruction at EL0.
[13]
Reserved, RES0.
I, [12]
Instruction cache enable. The possible values are:
0 Instruction caches disabled. This is the reset value.
1 Instruction caches enabled.
[11]
Reserved, RES1.
[10]
Reserved, RES0.
UMA, [9]
User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64.
The possible values of this bit are:
0 Disable access to the interrupt masks from EL0.
1 Enable access to the interrupt masks from EL0.
SED, [8]
SETEND instruction disable. The possible values are:
0 The SETEND instruction is enabled. This is the reset value.
1 The SETEND instruction is UNDEFINED.
ITD, [7]
IT instruction disable. The possible values are:
0 The IT instruction functionality is enabled. This is the reset value.
1 All encodings of the IT instruction with hw1[3:0]!=1000 are UNDEFINED and treated as
unallocated. All encodings of the subsequent instruction with the following values for
hw1 are UNDEFINED (and treated as unallocated):
11xxxxxxxxxxxxxx All 32-bit instructions, B(2), B(1), Undefined, SVC, Load/Store
multiple
1x11xxxxxxxxxxxx Miscellaneous 16-bit instructions
1x100xxxxxxxxxx ADD Rd, PC, #imm
01001xxxxxxxxxxx LDR Rd, [PC, #imm]
0100x1xxx1111xxx ADD(4),CMP(3), MOV, BX pc, BLX pc
010001xx1xxxx111 ADD(4),CMP(3), MOV
Contrary to the standard treatment of conditional UNDEFINED instructions in the Arm
architecture, in this case these instructions are always treated as UNDEFINED, regardless
of whether the instruction would pass or fail its condition codes as a result of being in
an IT block.
THEE, [6]
B2 AArch64 system registers
B2.90 System Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-527
Non-Confidential
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