Table B2-17 AArch64 implementation defined registers (continued)
Name Type Reset Width Description
CPUECTLR_EL1 RW
0x0000000000000000
64
B2.37 CPU Extended Control Register, EL1 on page B2-416
Mapped to a 64-bit AArch32 register.
CPUMERRSR_EL1 RW - 64
B2.38 CPU Memory Error Syndrome Register, EL1 on page B2-418
Mapped to a 64-bit AArch32 register.
L2MERRSR_EL1 RW - 64
B2.76 L2 Memory Error Syndrome Register, EL1 on page B2-493
Mapped to a 64-bit AArch32 register.
CBAR_EL1 RO - 64
B2.28 Configuration Base Address Register, EL1 on page B2-397
The reset value depends on the PERIPHBASE signal.
CDBGDR0_EL3 RO UNK 32 Cache Debug Data Register 0, see C5.1 About direct access to
internal memory on page C5-608.
CDBGDR1_EL3 RO UNK 32 Cache Debug Data Register 1, see C5.1 About direct access to
internal memory on page C5-608.
CDBGDR2_EL3 RO UNK 32 Cache Debug Data Register 2, see C5.1 About direct access to
internal memory on page C5-608.
CDBGDR3_EL3 RO UNK 32 Cache Debug Data Register 3, see C5.1 About direct access to
internal memory on page C5-608.
CDBGDCT_EL3 WO UNK 32 Cache Debug Data Cache Tag Read Operation Register, see
C5.1 About direct access to internal memory on page C5-608.
CDBGICT_EL3 WO UNK 32 Cache Debug Instruction Cache Tag Read Operation Register, see
C5.1 About direct access to internal memory on page C5-608.
CDBGDCD_EL3 WO UNK 32 Cache Debug Cache Debug Data Cache Data Read Operation
Register, see C5.1 About direct access to internal memory
on page C5-608.
CDBGICD_EL3 WO UNK 32 Cache Debug Instruction Cache Data Read Operation Register, see
C5.1 About direct access to internal memory on page C5-608.
CDBGTD_EL3 WO UNK 32 Cache Debug TLB Data Read Operation Register, see C5.1 About
direct access to internal memory on page C5-608.
B2 AArch64 system registers
B2.18 AArch64 Implementation defined registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-385
Non-Confidential
To Next Page
Loading...
