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ARM Cortex-A35

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Chapter C11
ETM registers
This chapter describes the ETM registers.
It contains the following sections:
C11.1 ETM register summary on page C11-733.
C11.2 Programming Control Register on page C11-736.
C11.3 Status Register on page C11-737.
C11.4 Trace Configuration Register on page C11-738.
C11.5 Branch Broadcast Control Register on page C11-740.
C11.6 Auxiliary Control Register on page C11-741.
C11.7 Event Control 0 Register on page C11-743.
C11.8 Event Control 1 Register on page C11-745.
C11.9 Stall Control Register on page C11-746.
C11.10 Global Timestamp Control Register on page C11-747.
C11.11 Synchronization Period Register on page C11-748.
C11.12 Cycle Count Control Register on page C11-749.
C11.13 Trace ID Register on page C11-750.
C11.14 ViewInst Main Control Register on page C11-751.
C11.15 ViewInst Include-Exclude Control Register on page C11-753.
C11.16 ViewInst Start-Stop Control Register on page C11-754.
C11.17 Sequencer State Transition Control Registers 0-2 on page C11-755.
C11.18 Sequencer Reset Control Register on page C11-757.
C11.19 Sequencer State Register on page C11-758.
C11.20 External Input Select Register on page C11-759.
C11.21 Counter Reload Value Registers 0-1 on page C11-760.
C11.22 Counter Control Register 0 on page C11-761.
C11.23 Counter Control Register 1 on page C11-763.
100236_0100_00_en
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-731
Non-Confidential

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