ARM Cortex-A35

Chapter C5
Direct access to internal memory
This chapter describes the direct access to internal memory that caches and TLBs use.
It contains the following sections:
• C5.1 About direct access to internal memory on page C5-608.
• C5.2 Encoding for tag and data in the L1 instruction cache on page C5-609.
• C5.3 Encoding for tag and data in the L1 data cache on page C5-610.
• C5.4 Encoding for the main TLB RAM on page C5-612.
• C5.5 Encoding for walk cache on page C5-617.
• C5.6 Encoding for IPA cache on page C5-618.
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