ARM ARM7TDMI - Nonsequential Cycles; Table 3-1 Bus Cycle Types

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Memory Interface

Bus cycle types are encoded on the nMREQ and SEQ signals as listed in Table 3-1.

A memory controller for the ARM7TDMI processor must commit to a memory access

only on an N-cycle or an S-cycle.

3.3.1 Nonsequential cycles

A nonsequential cycle is the simplest form of bus cycle, and occurs when the processor

requests a transfer to or from an address that is unrelated to the address used in the

preceding cycle. The memory controller must initiate a memory access to satisfy this

request.

The address class and (nMREQ and SEQ) signals that comprise an N-cycle are

broadcast on the bus. At the end of the next bus cycle the data is transferred between the

CPU and the memory. It is not uncommon for a memory system to require a longer

access time (extending the clock cycle) for nonsequential accesses. This is to allow time

for full address decoding or to latch both a row and column address into DRAM. This

is illustrated in Figure 3-2 on page 3-6.

Note

In Figure 3-2 on page 3-6, nMREQ and SEQ are highlighted where they are valid to

indicate the N-cycle.

Table 3-1 Bus cycle types

nMREQ SEQ Bus cycle type Description

0 0 N-cycle Nonsequential cycle

0 1 S-cycle Sequential cycle

1 0 I-cycle Internal cycle

1 1 C-cycle Coprocessor register transfer cycle

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