Debug in Depth
B-54 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
B.16 The debug status register
The debug status register is five bits wide. If it is accessed for a write, with the read/write
bit set, the status bits are written. If it is accessed for a read, with the read/write bit clear,
the status bits are read. The format of the debug status register is shown in Figure B-10.
Figure B-10 Debug status register format
The debug status register bit assignments are shown in Table B-9.
The structure of the debug control and status registers is shown in Figure B-11 on
page B-55.
4
TBIT
3
cgenL
2
IFEN
1
DBGRQ
0
DBGACK
Table B-9 Debug status register bit assignments
Bit Function
[4] Enables TBIT to be read. This enables the debugger to determine the processor
state and therefore which instructions to execute.
[3] Enables the state of the NMREQ signal from the core, synchronized to TCK,
to be read.
[2] Enables the state of the core interrupt enable signal, IFEN, to be read. This
enables the debugger to determine that a memory access from the debug state
has completed.
[1] Enable the value on the synchronized version of DBGRQ to be read.
[0] Enable the value on the synchronized version of DBGACK to be read.
To Next Page
Loading...
