Memory Interface
3-26 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Figure 3-19 Two-cycle memory access
3.6.4 Byte and halfword accesses
The processor indicates the size of a transfer by use of the MAS[1:0] signal as described
in MAS[1:0] on page 3-11.
Byte, halfword, and word accesses are described in:
• Reads
• Writes on page 3-27.
Reads
When a halfword or byte read is performed, a 32-bit memory system can return the
complete 32-bit word, and the processor extracts the valid halfword or byte field from
it. The fields extracted depend on the state of the BIGEND signal, which determines
the endian configuration of the system. See Memory formats on page 2-4.
A word read from 32-bit memory presents the word value on the whole data bus as listed
in Table 3-7 on page 3-27.
When connecting 8-bit to 16-bit memory systems to the processor, ensure that the data
is presented to the correct byte lanes on the core as listed in Table 3-7 on page 3-27.
MCLK
APE
nMREQ
SEQ
A[31:0]
nWAIT
D[7:0]
D[15:8]
BL[3:0] 0xF 0x2
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